A DARPA program manager described at DAC two new EDA research programs that aim to create the equivalent of a silicon compiler.
SAN JOSE, Calif. — The U.S. will pour $100 million into two research programs over the next four years to create the equivalent of a silicon compiler aimed at significantly lowering the barriers to design chips. The programs, involving 15 companies and more than 200 researchers, were described for the first time in a talk at the Design Automation Conference here.
The two programs are just part of the Electronics Resurgence Initiative (ERI) expected to receive $1.5 billion over the next five years to drive the U.S. electronics industry forward. ERI will disclose details of its other programs at an event in Silicon Valley in late July.
Congress recently added $150 million per year to ERI’s funding. The initiative, managed by the Defense Advanced Research Projects Agency (DARPA), announced on Monday that the July event will also include workshops to brainstorm ideas for future research programs in five areas ranging from artificial intelligence to photonics.
ERI used the stage of DAC to whet the industry’s appetite with what it is doing in areas related to EDA. The July event will be a coming-out party for projects in materials and chip architectures.
With $100 million in finding, the IDEAS and POSH programs represent “one of the biggest EDA research programs ever,” said Andreas Olofsson, who manages the two programs.
Together, they aim to combat the growing complexity and cost of designing chips, now approaching $500 million for a bleeding-edge SoC. Essentially, POSH aims to create an open-source library of silicon blocks, and IDEAS hopes to spawn a variety of open-source and commercial tools to automate testing of those blocks and knitting them into SoCs and printed circuit boards.
If successful, the programs “will change the economics of the industry,” enabling companies to design in relatively low-volume chips that would be prohibitive today. It could also open a door for designers working under secure regimes in the government to make their own SoCs targeting nanosecond latencies that are not commercially viable, said Olofsson.
“Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … but in software, it’s already happened with Linux. Sharing software costs was the best option for the industry, and we can share some hardware components, too.”
Olofsson called for embedding more expertise directly in design tools. The programs’ goals embrace more automated digital and analog tools for both chips and boards.
“I’ve designed a few boards and found it excruciating,” he said. “[Board designs quickly] explode into hundreds of details you have to worry about in resistors, capacitors, board size … and there are no optimization tools, so often, you have a sub-optimal solution. Given the number of boards designed every year, the upside here is enormous.”
Olofsson has first-hand experience in today’s design challenges. He designed a novel parallel processor as part of startup Adapteva. He also showed how design could be radically simplified as part of a million-dollar DARPA project that led to him accepting the job to head the two new programs.
The projects are scheduled for an interim release in 2020 aimed at producing chips not fully optimized for power, performance, and area. Final results are slated for 2022 and target quality comparable to traditional design teams.
Olofsson said that he is aware that the idea of a silicon compiler has been a Holy Grail for the semiconductor industry for decades. He noted that initial goals for 2020 are modest at only 50% of potential power/performance/area in part because the goal is so ambitious.
Currently, membership is restricted to partners that DARPA announced here. Long term, others can participate, especially in the open-source products, many of them from university researchers.
The two projects have 11 teams each with a total of 70 industry members. Companies participating include ADI, Arm, Cadence, Northrup Grumman, Nvidia, Qualcomm, and Xilinx.
“I imagine a few of these companies will have products here on the DAC floor in a few years,” he said.
Fifteen universities are also involved, contributing time from 44 professors and 99 grad students. They include Carnegie Mellon, The University of California at San Diego (UCSD), and the Universities of Illinois, Michigan, Texas, Utah, Virginia, and Washington.
Among the sub-projects, UCSD aims to design a complete open-source chip-design flow. The University of Washington will start an open-source library of IP blocks including a RISC-V platform. Xilinx aims to develop an open-source platform for mixed-signal emulation.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times
I'd be interested in more details about this project. I didn't quite understand the scope of the "silicon compiler". Does this involve some new sort of HDL? How would one incorporate the open-source cores?