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the_floating_ gate
The recent scanner problems on the 28-nm line indicate that the limits of many ...
the_floating_ gate
The 22-nm FinFET high-volume ramp-up is already more than two years behind ...
Feature dimension reduction slowdown
Handel Jones
3/20/2012 12:32 AM EDT
The semiconductor industry is facing the challenge that the two-year feature dimension cycle is over, and we are going into a highly unclear phase.
1. The 32/28-nm wafer volume ramp-up from the foundry vendors is already on a three-year cycle. 45/40-nm was at 10 percent of revenues in Q4/2009, and 32/28-nm will be at 10 percent in Q4/2012.
2. The 22-nm FinFET high-volume ramp-up is already more than two years behind 32-nm. FinFET is a difficult technology. The activities of Intel have been outstanding, but many additional challenges must be overcome to support the multi-threshold voltages and multiple VDD levels that are needed for SoCs.
3. Next-generation 20-nm planar CMOS will have a range of additional tolerance control challenges compared to 28-nm. One likely impact is that cost per gate at 20-nm will be higher than at 28-nm.
Figure 1- Cost per gate.
With the potential for increased cost per gate, additional compaction will need to be done, which will lengthen design completion times. Cost per gate at 14-nm can also be higher than that at 28-nm.
4. After 20-nmm, what is next? The semiconductor industry is committing to 14-nm FinFETs. There will, however, be many manufacturing challenges, including step coverage, control of the FIN dimensions, use of double patterning on multiple layers, and even the need for quad patterning.
EUV will clearly not be ready in the 2014 to 2015 time frame, so 193-nm tools need to continue being used.
The recent scanner problems on the 28-nm line indicate that the limits of many technologies are being reached.
Another key problem with FinFETs is the ability to have multiple VDD levels on the die as well as multi-threshold voltages.
New libraries will need to be developed, IP transitioned to the FinFET structures, test chips run, and production volumes ramped up. At 14-nm, complex chips will cost $200 million to $500 million to design, and re-spins will cost $20 million to $50 million. The cost of failure will increase dramatically.
What's more, 14-nm FinFETs are not likely to be in high-volume production outside of Intel until 2016 to 2017. High-volume production will require lower power consumption and lower cost per gate than earlier generations of technologies.
After 14-nm, there will be a range of new challenges (EUV, 450-mm, carbon nanotubes, etc). The semiconductor industry must be realistic that the supply challenges are becoming more difficult, and there will be a lengthening of the time to migrate to smaller feature dimensions.
The supply chain, which includes tooling vendors, reticle vendors, foundry vendors, IC product design companies and electronics products vendors, needs to adjust.
Apple has already adjusted in that the only real enhancement to the iPad from a hardware perspective is higher-resolution display.
With the capex cost of 10,000 wafers per month at $1 billion, the cost penalties for the wafer vendors will be very high if the appropriate adjustments are not made.
Handel Jones is the founder and CEO of market research and consulting firm International Business Strategies Inc.
1. The 32/28-nm wafer volume ramp-up from the foundry vendors is already on a three-year cycle. 45/40-nm was at 10 percent of revenues in Q4/2009, and 32/28-nm will be at 10 percent in Q4/2012.
2. The 22-nm FinFET high-volume ramp-up is already more than two years behind 32-nm. FinFET is a difficult technology. The activities of Intel have been outstanding, but many additional challenges must be overcome to support the multi-threshold voltages and multiple VDD levels that are needed for SoCs.
3. Next-generation 20-nm planar CMOS will have a range of additional tolerance control challenges compared to 28-nm. One likely impact is that cost per gate at 20-nm will be higher than at 28-nm.
Figure 1- Cost per gate.
With the potential for increased cost per gate, additional compaction will need to be done, which will lengthen design completion times. Cost per gate at 14-nm can also be higher than that at 28-nm.
4. After 20-nmm, what is next? The semiconductor industry is committing to 14-nm FinFETs. There will, however, be many manufacturing challenges, including step coverage, control of the FIN dimensions, use of double patterning on multiple layers, and even the need for quad patterning.
EUV will clearly not be ready in the 2014 to 2015 time frame, so 193-nm tools need to continue being used.
The recent scanner problems on the 28-nm line indicate that the limits of many technologies are being reached.
Another key problem with FinFETs is the ability to have multiple VDD levels on the die as well as multi-threshold voltages.
New libraries will need to be developed, IP transitioned to the FinFET structures, test chips run, and production volumes ramped up. At 14-nm, complex chips will cost $200 million to $500 million to design, and re-spins will cost $20 million to $50 million. The cost of failure will increase dramatically.
What's more, 14-nm FinFETs are not likely to be in high-volume production outside of Intel until 2016 to 2017. High-volume production will require lower power consumption and lower cost per gate than earlier generations of technologies.
After 14-nm, there will be a range of new challenges (EUV, 450-mm, carbon nanotubes, etc). The semiconductor industry must be realistic that the supply challenges are becoming more difficult, and there will be a lengthening of the time to migrate to smaller feature dimensions.
The supply chain, which includes tooling vendors, reticle vendors, foundry vendors, IC product design companies and electronics products vendors, needs to adjust.
Apple has already adjusted in that the only real enhancement to the iPad from a hardware perspective is higher-resolution display.
With the capex cost of 10,000 wafers per month at $1 billion, the cost penalties for the wafer vendors will be very high if the appropriate adjustments are not made.
Handel Jones is the founder and CEO of market research and consulting firm International Business Strategies Inc.
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rick.merritt
3/20/2012 2:17 AM EDT
I'm glad someone is finally laying this all out publicly.
A decade ago, Gordon Moore told me his "Law" would slow down before we hit the end as we approached the size of silicon atoms. Well, we're seeing the slow down, Mr. Moore.
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Or_Bach
3/20/2012 3:59 AM EDT
Yes, the reality is very clear. The cost for 0.7x next generation scaling is escalating too scary numbers for all aspects:Fab cost,process R&D;,EDA and libraries,Chip design,mask set,...
But that is not the only option to continue advance semiconductor devices. We can keep Moore's Law using the recent breakthrough of monolithic 3D http://www.monolithic3d.com. Clearly most of the NAND vendors already going to that direction.
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resistion
3/20/2012 11:11 AM EDT
I would remind only some layers would be effectively doubled, e.g. gate, active, metal1, contact. If you're only adding 10% more layers, but shrinking to 60% area, you're still cost-effective, just less so than previous node shrinks.
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daleste
3/20/2012 9:39 PM EDT
The easy shrinks of silicon have already been done. As it gets harder for each next step, eventually we all knew that it would become less economical to make that step than to stay where we are. We may be at that point, but there will still be innovation that will create cost savings as we go forward. It just may not be as dramatic.
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any1
3/21/2012 8:57 AM EDT
The problem is that the semiconductor business model has been broken for many years now. The end of Moores law makes it even worse for large leading edge manufactures and equipment vendors as return on investment shrinks with each new process node.
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the_floating_ gate
3/22/2012 1:11 AM EDT
The 22-nm FinFET high-volume ramp-up is already more than two years behind 32-nm.
The FinFET is NOT planar - by going FinFET Intel actually accelerated Moore' law.
There is Moore law
and there is capital intensity which is increasing.
Now it's becoming more and more about fix cost absorption:
a fast, clean ramp will become super crucial/ mandatory.
Here's Intels litho roadmap
http://www.electroiq.com/articles/sst/2012/02/spie-advanced-lithography-intel-tsmc-tool-roadmap-takeaways.html
Apple has already adjusted in that the only real enhancement to the iPad from a hardware perspective is higher-resolution display.
That's rediculous:
Apple's A5X uses the same 45nm process used on the original Ipad - one difference is that the A5X chip is 3x the size compared to the original A4 - talking about cost per gate....
IOW that means they need 3 x wafers to get the same number of dies - what a business model
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the_floating_ gate
3/22/2012 1:49 AM EDT
The recent scanner problems on the 28-nm line indicate that the limits of many technologies are being reached.
What scanner problems - please explain
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